Organic substrates for example printed circuit boards and chip carriers have been and continue to be developed for many applications. These are expected to displace ceramic substrates, in particular in many chip carrier applications, because of reduced cost and enhanced electrical performance. The use of a multi-layered interconnect structure such as an organic chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges, one of which is the reliability of the connection joints between the semiconductor chip and the organic chip carrier and another of which is the reliability of the connection joints between the organic chip carrier and the printed circuit board.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects are the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier can exhibit high stress during operation (thermal cycling). Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board can also exhibit high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically a semiconductor chip has a CTE of 2–3 parts per million per degree Celsius (ppm/° C.) while a standard printed circuit board has a much greater CTE of 17–20 ppm/° C.
It is therefore desirable to reliably interconnect a semiconductor chip to a printed circuit substrate or board in a fashion that significantly improves electrical performance. An electronic package that includes a multi-layered interconnect structure, an organic chip carrier that is relatively compliant and made by selecting the materials and thickness of the materials to yield a chip carrier CTE of only about 10–12 ppm/° C., can substantially prevent failure of the interconnections between the semiconductor chip and the organic chip carrier and between the organic chip carrier and the printed circuit board. Furthermore, it can enable design of the electronic package to significantly improve electrical performance. It is believed that such a structure and method for making same would constitute a significant art advancement.